Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to an internal clock signal generation circuit for generating an internal clock signal, and a method for operating the same.
Generally, a semiconductor device, including a Double Data Rate Synchronous DRAM (DDR SDRAM), receives an external clock signal to generate an internal clock signal, and uses the generated internal clock signal as a reference for a synchronization of various operations within the semiconductor device. Therefore, the internal clock signal generation circuit for generating the internal clock signal is included in the semiconductor device. Examples of the internal clock signal generation circuit include a Delay Locked Loop (DLL) and a Phase Locked Loop (PLL). Hereinafter, for the sake of convenience, reference is only made to the delay locked loop.
FIG. 1 is a block diagram of a conventional delay locked loop.
Referring to FIG. 1, the conventional delay locked loop includes a variable delay unit 110, a delay replica modeling unit 120, a phase detection unit 130, and a control signal generation unit 140.
The variable delay unit 110 is configured to delay an external clock signal CLK_EXT by a time corresponding to delay control signals SH0 to SHN (where N is a positive integer) to generate a DLL clock signal CLK_DLL. The generated DLL clock signal CLK_DLL is inputted to the delay replica modeling unit 120. A clock path and a data path within the semiconductor device are modeled in the delay replica modeling unit 120. The DLL clock signal CLK_DLL is delayed by a modeled time of the delay replica modeling unit 120 and is outputted as a feedback clock signal CLK_FED. The phase detection unit 130 is configured to compare a phase of the external clock signal CLK_EXT with a phase of the feedback clock signal CLK_FED, and generate a phase detection signal DET_PHS corresponding to the comparison result. The control signal generation unit 140 is configured to generate the delay control signals SH0 to SHN in response to the phase detection signal DET_PHS. The delay control signals SH0 to SHN generated in this manner are used to control the delay amount applied to the variable delay unit 110.
Generally, the variable delay unit 110 is implemented with a plurality of unit delay cells. Each of the unit delay cells has a predetermined delay time (hereinafter, referred to as a unit delay time). Herein, the unit delay time is determined in the design stage.
According to the above-mentioned structure, the conventional delay locked loop generates the delay control signals SH0 to SHN which synchronize the phases of the external clock signal CLK_EXT with the feedback clock signal CLK_FED, and generates the DLL clock signal CLK_DLL corresponding to the delay control signals SH0 to SHN. Herein, a state where two phases are synchronized with each other is called ‘locking’. When a locking operation is completed, the DLL clock signal CLK_DLL is transferred to a data output circuit, and data are outputted in synchronization with the transferred DLL clock signal CLK_DLL. The data outputted in synchronization with the DLL clock signal act as if they are outputted in synchronization with the external clock signal CLK_EXT.
Meanwhile, the conventional delay locked loop has a typical slowdown concern in the locking operation when the external clock signal CLK_EXT has a low frequency. That is, while the delay time that the variable delay unit 110 should provide is increased in response to the low-frequency external clock signal CLK_EXT, the unit delay time of the unit delay cell is too small. Of course, this concern may be addressed by designing the unit delay cell to have a greater unit delay time necessary to prepare for the low-frequency external clock signal CLK_EXT. However, this method does not guarantee a desired locking operation in the case of a high-frequency external clock signal CLK_EXT.